The present invention relates to processor cache management, and more specifically, to the cache coherence in a multi-processor or multi-processor core system.
In multi-processor (or multi-core) systems, multiple processing elements operate at the same time. Therefore, it is possible that they simultaneously access the same memory line. Provided none of the processing elements changes the data in this memory line, they can share it indefinitely and cache it as they please. But as soon as one processing element updates the location, the other processing elements might work on an out-of-date copy that, for example, resides in their respective local cache. Consequently, to maintain coherence a process notifies all the processing elements of changes to a shared memory lines. Said process is referred to as “cache coherence protocol”, “cc-protocol” or “memory coherence protocol”.
In some systems, the performance of the cache coherence protocol constitutes a performance bottleneck. In some systems it would be desirable to reduce the size and cost of the hardware implementing the cache coherence protocol.